1. Technical Field
The present invention relates in general to designing and simulating digital devices, modules and systems. In particular, the present invention relates to a method and system that improve the model build and simulation processes in order to allow a designer to easily instrument and monitor a simulation model. More particularly, the present invention relates to uniquely naming specified simulation model events within hardware description language simulation models.
2. Description of the Related Art
Verifying the logical correctness of a digital design and debugging the design, if necessary, are important steps in most digital design processes. In a typical automated design process that is supported by a conventional electronic computer-aided design (ECAD) system, a designer enters a high-level description utilizing a hardware description language (HDL), such as VHDL, producing a representation of the various circuit blocks and their interconnections. The ECAD system compiles the design description into a format that is best suited for simulation. A simulator is then utilized to verify the logical correctness of the design prior to developing a circuit layout.
A simulator is typically a software tool that processes a digital representation, or simulation model of a circuit, together with a list of input stimuli representing inputs of the digital system. The simulator generates a numerical representation of the circuit response that may then either be viewed on the display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. The simulator may be run either on a general-purpose computer or on another piece of electronic apparatus specially designed for simulation. Simulators that run entirely in software on a general-purpose computer are often referred to as “software simulators”. Simulators that are run with the assistance of specially designed electronic apparatus are often referred to as “hardware simulators.”
VHDL is a higher-level language utilized for describing the hardware design of complex devices. The overall circuit design is frequently divided into smaller parts (hereinafter referred to as design entities) that are individually designed, often by different design engineers, and then combined in a hierarchical manner to create an overall model. This hierarchical design technique is very useful in managing the enormous complexity of the overall design. Another advantage of this approach is that errors in a design entity are easier to detect when that entity is simulated in isolation.
Digital systems are often designed by large numbers of persons that are distributed over a wide geographic area, often times in different countries. Moreover, software design entities for such digital systems are commonly taken from previous design projects in which the original design team is no longer available.
For proper assembly and testing of a simulation model design, it is necessary to assemble the various model components without naming conflicts. A potential conflict arises in the choice of names for specified simulation events. If a model component re-uses an event name, a name collision may occur that can impair model construction and testing.
Conventionally, this problem is often addressed by adopting a particular naming convention. A naming convention is a set of agreed-upon rules that requires each designer to name events according to a defined procedure that prevents collisions of event names among the various parts of a model.
Most conventional naming conventions share two inherent shortcomings. First, many naming conventions rely on the individual compliance of designers, and failures to comply are not detected until assembly of the overall model is underway. The second problem with convention naming conventions is that when components from a project are re-used in a future project, the naming convention used in the previous project may or may not be compatible with the future project.
From the foregoing it can be appreciated that a need exists for an improved data structure for simulation model events that would prevent name collisions and that would allow events to be considered with or without regard to the replication of events due to the repeated instantiation of a particular target design entity.